A typical battery pack used in portable electronic apparatuses includes a plurality of bare cells, a protective circuit module (PCM) in which a protective circuit for controlling the charge and discharge of the bare cells is formed, and a terminal line for electrically connecting the bare cells and the protective circuit to each other. The bare cells, the PCM, and the terminal line can be accommodated in a predetermined case.
The charge management system and battery protection IC offer extensive battery over-voltage and over-current protection, battery pre-conditioning and one percent charger voltage accuracy. They are paced in a small thermally enhanced lead frame package which may be a small surface mount device (SMD).
Conventional technologies to further reduce the size of battery protection integrated circuit (IC) are challenged by several technical difficulties and limitations. Conventional battery protection IC typically includes a power control IC and integrated dual common-drain metal oxide semiconductor field effect transistors (MOSFETs), which are packed in a lead frame package with a small foot print of a size as small as 2×5 mm. FIG. 1 is a circuit diagram illustrating a battery protection IC package of the prior art and FIG. 2 is a top view of a battery package assembly of FIG. 1.
As shown in FIG. 1, a protective circuit module 100 may include a power control IC 102 and dual common-drain MOSFETs 106 and 108 that are co-packed in a module package. In FIG.1 VCC indicates an input supply pin that may be connected to the anode of a battery, e.g., a lithium-ion or lithium polymer battery cell, via a resistor. VSS indicates a ground pin that may be connected to a source S1 of an internal discharge MOSFET 106 and the cathode of the battery. VM indicates an over-charge and charger voltage monitor pin. OUTM indicates an output pin that may be connected to a source S2 of an internal charge MOSFET 108. DO and CO indicate pins of the power control IC 102 that may be connected the gate of the discharge MOSFET 106 and gate of charge MOSFET 108 respectively. MOSFETs 106 and 108 may be dual common-drain MOSFETs that are fabricated on single semiconductor chip with the same drain pad for drains D1 and D2 but distinct source and gate pads. A current-limiting resister R1 forms a low pass filter with a capacitor C1 to reduce supply voltage fluctuation. A resistor R2 provides ESD protection and current-limiting capability in the event of reverse charging. Capacitor C1 and both resistors R1 and R2 may be located outside the package 100. Pins VM and VCC of the control IC 102 may be electrically connected to the VM and VCC pins of the circuit module 100. The source voltage input VSS of the control IC 102 may be connected to the VSS pin of the circuit module 100.
The power control IC 102 may be positioned on a lead frame die pad 112 and integrated dual common-drain MOSFETs 106 and 108 may be positioned on another die pad 104. Two die pads 104 and 112 may be included in a lead frame package. Connections between the electrodes and leads in the circuit shown in FIG. 1 may be furnished by bond wires. To minimize the parasitic effect of bond wires the VSS lead and VCC lead of the lead frame package may be located on opposite sites of the package, which is not a preferred pin layout when the package is attached onto a printed circuit board. In this prior art package, because the power control IC 102 and dual common-drain MOSFETs 106 and 108 are attached onto two separate die pads, and because the control IC 102 requires a finite size of die pad 112 for attaching the IC, the available size for die pad 104 to accommodate the dual common-drain MOSFETs 106 and 108 of possibly maximum size is further limited for a lead frame package of a given footprint size, which may further result in increase in turn-on resistance of the dual common-drain MOSFETs. The size of the lead frame package is typically about 2 mm×5 mm.
Best performance for the battery protection package is conventionally achieved by using the largest possible MOSFET die size to minimize the drain to source turn-on resistance (Rds-on). However, the power control IC 102 also takes up space on the lead frame, which limits the space available for the MOSFETs 106 and 108. Only relatively small MOSFETs, typically having a maximum drain to source resistance of about 48-60 mΩ including the resistance of bond wires to the MOSFETs, tend to fit in a 2×5 mm lead frame package. This reduces the efficiency of a power management package in this size range. If a lower turn-on resistance is desired, a package with preferably larger footprint is needed to meet the requirement.
It is within this context that embodiments of the present invention arise. It would be desirable to develop a package which would use the same or smaller package for integrated dual common-drain MOSFETs with lager size and smaller Rds-on. It would be further desirable to produce such a package with a thinner package thickness. It would also be desirable to bring the VSS and VCC pins of the package on the same side of the package which is preferable for application usage.